Magnetic counter circuits



y 1960 J. P. ECKERT, JR 2,944,161

MAGNETIC COUNTER CIRCUITS Filed Aug. 6, 1954 ll Sheets-Sheet 1 B(Flux Dansify) l2 FIG. flag s 20 r P P V 2| Jar 7 (Muqnefizing Force) p Amp. (See lg.

37 J l 32 I Output lnvnrter 36 J i EH I'L Del Stop Inpui Wire F 0 Wire G 2 Wm H o Wire J And c Outpuf Time Period Tl 1'2 T5 T4 Tu n 1'? Ta 1': no ru m m 114 'ns nan-1m m mom rzzrzsraonflms Tzfi INVENTOR JOHN PRESPER EOKERT, JR.

ATTORNEY July 5, 1960 J. P. ECKERT, JR

MAGNETIC COUNTER CIRCUITS ll Sheets-Sheet 2 Filed Aug. 6, 1954 mm T 2: WINII llllllll INVENTOR mm 6E JOHN PRESPER EOIGRTJF ATTORNEY July 5, 1960 J. P. ECKERT, JR 2,944,161

MAGNETIC COUNTER CIRCUITS Filed Aug. 6, 1954 11 Sheets-Sheet 3 Gate 40 A 45 47 j Amp 2 44 (See F|g.2 ou'pu' 54 y l I Deluy GM U Step Input ATTORNEY July 5, 1960 J. P. ECKERT, JR

MAGNETIC COUNTER CIRCUITS ll Sheets-Sheet 4 Filed Aug. 6, 1954 qm GE I. QI

INVENTOR JOHN PRESPER EOKERT, JR.

35am 52w ATTORNEY July 5, 1960 C J. P. ECKERT, JR 2,944,161

MAGNETIC COUNTER CIRCUITS Filed Aug. 6, 1954 11 Sheets-Sheet 5 63c, 63d,afc. FIG. 6B. Input mg"- m 62 2 Amp.

600 God GOQGULOM. lnverter I Erin 2| Inverted Output Ouipui 73% 75b 8/.- JLJOC 7 I my z 1 =1 m y/.1. Jk- 4 5 ma 1 c 7 FIG. 7.

INVENTOR JOHN PRESPER EGKERT, JR.

ATTORNEY y 1950 .1. P. ECKERT, JR 2,944,161

MAGNETIC COUNTER CIRCUITS Filed Aug. 6, 1954 ll Sheets-Sheet 6 82c put 8 ar. j

2/ W Source 900 3 96 i +2V Source 90b +V Source 900 f7 FIG- 944. INVENTOR RT JR. Source 900 0 JOHN PRESPEEGKE 'f2\ 1 Source 9C6 ATTORNE July 5, 1960 J. P. ECKERT, JR 2,944,161

MAGNETIC COUNTER cmcun's Filed Aug. 6, 1954 11 Sheets-Sheet 7 lout mQJ +10%]: FIG. /0.

Cur rent Waveform Source 1006 Current Waveform Souru lOl d Step Input Source lOlg Source IOOg FIG. IOA.

INVENTOR JOHN PRESPER E OKE RT, JR.

ATTORNEY J. P. ECKERT, JR 2,944,161

MAGNETIC COUNTER CIRCUITS ll Sheets-Sheet 9 July 5, 1960 Filed Aug. 6, 1954 ATTORNEY July 5, 1960 J. P. ECKERT, JR

MAGNETIC COUNTER cmcuns l1 Sheets-Sheet 11 Filed Aug. 6, 1954 u a E l. n w m wi m m m 4 w I- 3 w m H M's; m l I F K k j m m w. m 5 w INVENTOR ATTORNEY Stats nine MAGNETIC COUNTER CIRCUITS Filed Aug. 6, 1954, Ser. No. 448,206

31 Claims. (Cl. '307-88) This invention relates to counter circuits and more particularly to counter circuits of the type used in electronic computers.

The primary object of this invention is to provide a counter circuit utilizing magnetic amplifiers whereby the advantage of that type of component is achieved.

Another object of this invention is to provide a counter circuit in which the component parts are not as likely to burn out as in the circuits of the prior art.

An additional object of this invention is to provide a magnetic counter circuit that is low in cost.

Still another object of this invention is to provide a counter circuit that may be placed in a very small space.

In addition, it is an object of the invention to provide a counter circuit that is very efiicient and effective in operation.

Briefly speaking, the invention employs the combination of a magnetic amplifier and means whereby the amplifier acts as a flip-flop circuit, and one or more gates, all so combined as to produce a counter circuit in which there is one output signal for every two input signals. Various modifications in the circuit for combining the aforesaid elements are hereinafter described.

In the drawings:

Figure 1 is an idealized hysteresis loop of the material used in the cores of the magnetic amplifiers.

Figure 2 is a schematic diagram of a non-complementing amplifier of a type which may be employed in connection with the invention.

Figure 3 is a block diagram of one form of the invention.

Figure 3A is a waveform diagram of the device of Figure 3.

Figure 3B is a schematic diagram of the combination of Figure 3.

Figure 4-is a block diagram of a modified form of this invention.

Figure 5 is a block diagram of another modified for of this invention.

Figure 6 is a schematic diagram of yet another form of this invention.

Figure 6A is a waveform diagram of the power pulses of Figure 6.

Figure 6B is a block diagram of the circuit of Figure 6.

Figure 7 is a schematic diagram of a modified form of the invent-ion.

Figure 8 is a schematic diagram of a further rnodified form of the invention.

Figure 9 is a schematic diagram of another modified form of the invention using complementing magnetic amplifiers.

Figure 9A is a timing diagram of the device of Figure 9.

Figure 10 is a schematic diagram of still another modified form of the invention in which transformer action is employed.

Figure 10A is a timing diagram of the device of Figure 10.

Figure 11 is a block diagram of a modified form of the invention in which a long delay line insures that 2,944,161 Patented July 5, 1960 the device remains in one stable state at least a predetermined time before it can be flipped to another by the next step input pulse.

Figure 111A is a modified form of the device of Figure l1. 1

Figure 12 is a schematic diagram of the device of Figure 11.

Figure 13 is a schematic diagram of a non-complementing parallel type magnetic amplifier.

Figure 14 is a schematic diagram of a magnetic counter circuit employing a non-complementing parallel type mag- Figure 14A is a waveform diagram showing the relative waveforms of the pulse generators of Figure 14.

Figure 15 is a schematic diagram of a complementing parallel type magnetic amplifier.

Figure 16 is a schematic diagram of a magnetic counter circuit employing the amplifier of Figure 15.

The present application .utilizes magnetic amplifiers of the general types described in the following two applications. Theodore H. Bonn and Robert D. Torrey, Serial No. 402,858, filed January 8, 1954, entitled, Signal Translating Device; and John Presper Eckert, Jr. and Theodore H. Bonn, Serial No. 382,180, filed September 24, 1953, entitled Signal Translating Device. These applications are assigned to the assignee of the present application.

Generally speaking, there are four types of magnetic amplifiers which may be employed in connection with this invention, as follows:

(1) Non-complementing series amplifiers of which Figure 2 is a typical illustration. Figures 3, 3B, 4, 5, 6, 7, 8, 11, 11A and 12, illustrate magnetic counter circuits employing non-complementing series amplifiers.

(2) Complementing series amplifiers. -An amplifier of this type is one in which an uninterrupted train of power pulses normally flows through a winding on the core to the load but which is interrupted by aninput pulse occurring between pulses of the series. A magnetic counter circuit using such an amplifier is shown in Figure 9.

(3) A non-complementing parallel amplifier of the type shown in Figures 10 and 13. A magnetic counter circuit employing this type of magnetic amplifier is illus trated in Figures '10 and 14. g

(4) A complementing parallel type amplifier, as shown in Figure 1-5. A magnetic counter circuit employing this type of magnetic amplifier is shown in Figure 16.

Figure 1 illustrates the hysteresis loop for the bistable state core C of the magnetic amplifier of Figure 2.v The core may .be made of a variety of materials,.among which are the various types of ferrites and the various magnetic tapes, including Orthonik and 4-79 Moly- Permalloy. These materials may have different heat treatments to give them different properties. The magnetic material employed in the core should preferably, though not necessarily, have a substantially rectangular hysteresis loop (as shown in Figure 1). Cores. of this character are now well known in the art. In addition to the wide variety of materials available, the core may be constructed in a number of geometries including both closed and open paths; for example, cup-shaped, strips, and toroidal-shaped cores are possible. Those skilled in the art understand that when the core is operating on the horizontal (or substantially saturated) portions of the hysteresis loop, the core is generally similar in operation to an air core in that the coil on the core is of low impedance. On the other hand, when the core is operating on the vertical (or unsaturated) portions of the hysteresis loop, the impedance of the coils on the core Will be high.

fier 21 are similar to those shown on the top horizontal 1 line of Figure 3A; Rectifier 21 is used when source 24B is an alternating current. source, whereby only positive halves of the cycle appear, as shown, in said top line of said Figure 3A. The signal source 27 produces from time to time the control signals and by reason of any suitable means S, these control signals are always synchronized to appear during spaces between the power pulses. When the power pulses from source 2t? are positive they pass through rectifierZl, coil 22, resistor 27 to negative pole 2 4 which is below ground potential. If we assume that at the start of the first pulse the core was residing at a stable state represented by point 14 on its hysteresis loop (see Figure 1), it will be driven to point 15. At the end of this pulse, it will return to and reside in a second stable state represented by zero value 11. At the conclusion of the first pulse, current will flow in the following circuit: from ground to rectifier 26, coil 2'2, resistor 23 to negative pole 24. This is a current flow through coil 22 in the opposite direction from that of the first pulse and drives the core negatively from point ill to point 13. At the conclusion of this reverse pulse, the second power pulse will again drive the core positively from point 13 through point 14 to point 15, and from thence it will go to 11, after the conclusion of the second pulse. The next action will be another flow of current in the following circuit: from ground, rectifier 26, coil 22, resistor23, to negative pole 24.

Hence, the magnetization of the core will repeatedly traverse the hysteresis loop and the majority of the time the core will be operating on unsaturated portions of the hysteresis loop, consequently there 'will be substantially no output. If, however, an input signal is received in coil 25, at a time when the core is at point 11, the reverse current (in circuit: ground 264246 24) will not drive the core negatively to point 13 as usual. In such situation, there will be two opposite magnetizing forces on the core. n the one hand, there will be a flow of current in the circuit: ground to rectifier 26, coil 22, resistor 23, to negative pole 24, tending to apply a negative magnetizing force to the core. There will be an additional input current in coil 25 tending to apply a positive magnetizing force to the core. These two magnetizing forces will cancel each other and the core will remain at point 111 on the hysteresis loop. Consequently, the next power pulsewill pass through rectifier 21 and coil 22 to the output. It will drive the core from point 11 to point 12 on the hysteresis loop. The core is substantially saturated 7 throughout this entire period, and therefore a large pulse output will appear. The operation of the non-complementing amplifier may be summarized by stating that the currents will drive the core around-the hysteresis loop without'substant-ial saturation and therefore without any substantial pulse output until there is a current flow through coil 25. This will stop the alternating magnetizations of the core, allowing the next power pulse to saturate the core and give a large output.

Figure 3 is a block diagram of a counter circuit embody-ing the invention. The step input (or trigger pulse source 30 supplies pulses from time to time, which are to be counted. Gate 31 allows a signal to flow from the step input 30 to the amplifier 35 whenever it receives a signal from inverter 32 concurrently with the step input signal. Both inverters 32 and 33 are so constructed and arranged, as hereinafter described in more detail, that theyhave a signal level at their respective outputs whenever there is no signal pulse at their respective inputs, and similarly there are low level signals attheirrespective outputs when there are pulse signals at their respective inputs. Gate 34 allows any signal from the inverter 33 to pass to the amplifier 35 if there is a control signal applied to the gate 34 by the delay line 36, provided the signal from the delay line 36 arrives con currently with the signal from the inverter 33. The amplifier 35 includm working parts of the apparatus shown in Figure 2 except for the signal source 27.

The operation of the device of Figure 3 can be most readily understood by referenceto the Waveform' diagram of Figure 3A where there is shown an uninterrupted train of equally spaced power pulses PP which are produced by the source 20 (Figure 2). The device of Figure 3 has two stable states, in one of which the output 37 is characterized by a plurality of equally spaced pulses. In the other stable state there is no output pulse at 37. Assuming at the start of the apparatus that there is no output pulse at terminal 37, there is consequently no signal pulse being fed into delay line 36 and hence no signal pulse at the input of inverter 32. Consequently, since the inverter has a high level output whenever there is no input pulse thereto, there will be a constant high potential on wire G, as shown in Figure 3A. On the other hand, there will be a low potential on wire H and consequently gate 34 will be closed. Assuming that there are no pulse signals at the step input, there will be no current to pass through gate 31, and since there is no input pulse to inverter 33 there will be a constant positive output potential therefrom as shown in Figure 3A.

If we assume that this situation continues for seven equally spaced time periods T1 to T7 inclusive (Figure 3A), the potentials applicable to those seven time periods will be as shown in Figure 3A. If it be assumed that at time period T8 the first input pulse appears at wire 30, it Will pass through gate '31 since there is a positive potential on wire G, and will produce an output from amplifier 35 at time period T9. The reason that the output of amplifier 35 is delayed one space from its input is ob vious from a study of the description of Figure 2 which has already been given. The output pulse on wire I at time T9 is delayed by delay line 36 for one time period and therefore appears at time Tit as a pulse on wire H. The potential on wire H opens gate 34 to the potential at the output of inverter 33, which rose to a positive value at the termination of time period T8 and remained positive until the next pulse on input 39. Hence, at time period T10 the positive output of inverter 33 passes through gate 34 to the input of amplifier 35 which causes a power pulse to appear'at wire I at. time T1 1. The latter pulse is delayed for one time period and therefore appears at wire H at time period T12. This potential on wire H again opens gate 34 and allows current from inverter 33 to flow to amplifier 35 at time period T12, thereby creating another pulse in the output of amplifier 35at time period T13 which is delayed by delay means 36 and appears on wire H at time period T14. This potential on wire H again opens gate 34- and inverter 33 thereupon feeds another pulse to the input of amplifier at time period T14, thereby producing another pulse at output I at time period T15 which is delayed by delay means 36 and appears at wire H at time period T16. At time period T16 there appears another pulse at step input 30 which is inverted by inverter 33 and therefore there is no output from that inverter. Consequently, at

time period T16 no current can flow through either of gates 31 or 34-. Current cannot flow through gate 31 because the potential at the output of inverter 32 on Wire Current cannot pass through gate 34-, for

G is zero. although this gate is opened by'reason of potential on wire H, there is no potential on wire F and therefore nothing to pass through the gate to the amplifier 35. Consequently, the input of amplifier 35 is not energized at time period T16 and consequently no output appears therefrom at time period T17. Hence, the potential on wire H drops to zero and gate 34 is closed, thus preventing any further potential from the inverter 33 from passing to the amplifier 35. The gate 31 is opened by reason of potential on wire G but since there is no step input pulse on wire A there is no current flow to the amplifier 35. This situation continues to exist as long as there is no further step input pulse, in other words it continues from time period T17 through time period T21. At time period T22 another pulse appears on step input 30 which can now pass through gate 31 which is opened by reason of the potential on wire G and'flows to amplifier 35. Hence, there is an output pulse on wire I at time period T23 which is delayed and appears on wire H at time period T24. By reason of inverter 32, however, the gate 31 'isclose'd at time period T24. Hence, although there is another step inputpulse on input 30 at time T24, no current can flow through the gate 31 by reason of the absence of potential on wire G. Likewise, no potential will pass through gate 34 since the presence of the signal attime T24 on the input of inverter. 33reduced the potential of its output to zero. Hence, starting with time period T25 and ending with the next input pulse, there are no output pulses on wire 37.

The result of Figure 3A may be analyzed by stating that the input pulse at time period T8 caused the device to shift into one stable state of operation in which it produced an output pulse corresponding to each power pulse. In other words, at time periods T9, T11, T13 and T15, there were pulses in the output. These pulses Would'have continued indefinitely in the absence of another pulse at the step input30. The second pulse on step input 30 stopped the appearance of pulses in the output and they remained stopped until the third input pulse at step input 30 again started the appearance of output pulses at wire I. The fourth step input pulse again stopped the appearance of power pulses. Hence, there will be an uninterrupted train of power pulses in the output between the first and second, the third and fourth, the fifth and sixth, etc. input pulses, and there will be no pulses in the output during the periods between the second and third, fourth and fifth, sixth and seventh, etc. step input pulses. If, therefore, an uninterrupted train of power pulses is considered as a group and regarded as a single output indication, there will be one output for every two input pulses.

Figure 3B is a schematic diagram of the apparatus of Figure 3. The wires A, B, D, E, F, G, H and J of Figure 3 correspond to the wires bearing similar letters in Figure 3B. In Figure 313 if we assume the state of affairs shown in Figure 3A to persist from time period T1 to T7, the several parts of Figure 3B will be operating as follows over that time period. It is assumed that the pulses from step input 30 are positive and that the lower end of resistor 31a is connected to a source of negative potential far below ground. Likewise the upper end of resistor 31a is connected to a source of positive potential far above ground. In the absence of a signal on wire A, current will flow from the positive pole 31e to the negative pole '31 and the connection 31g as well as wire D, will stand at substantially ground potential. In the event of a positive pulse appearing on wire A, the upper end of resistor 31d will become positive and rectifier 31b will be cut off whereby the Wire D will conduct current from the source 31e, unless the potential induced in the secondary 32a of the inverter transformer compensates the bias battery potential 320. In that case, the cathode of rectifier 31c is efiectively grounded whereby wire D is effectively grounded and there will be no current in that wire. In other words, the only condition whereby there is an output in wire D is that there is no potential induced in the secondary 32a of the inverter transformer whereby the battery 32c raises the potential at the cathode of rectifier 31c and cuts off this rectifier; and further that there is a positive potential on wire A toYcut otf rectifier 31b. In event of a coincidence of those two factors, a current will flow from pole 31e to wire D.

Current pulses on wire D have substantially the same wave shape as the step input pulses and appear during the spaces between power pulses. The latter is insured by any suitable'means S connecting the source 20 with the step input 30. In accordance with the previous description of Figure 2, any pulse appearing on wire D will create a pulse on wire I one time period later. The delay means 36 may be of any suitable form, for example, a delay line (or in fact another magnetic amplifier), and will delay any pulse on wire I by one time period and apply the same to wire H. The inverter 32 may be simply a transformer with a source of bias in series with its secondary. However, any other type of inverter, for example, a complementing magnetic amplifier, may be used. The inverter 32 functions as follows. Normally the battery 32c applies a potential which tends to cut off the rectifier 31c. However, upon appearance of a pulse on primary 3212, the output 320: of the transformer neutralizes the potential of battery 32c and thus effectively grounds thecathode of rectifier 31c. transformer is preferably a so-called pulse transformer, that is one capable of reproducing a substantially squarewave input pulse in its output.

Reference is now made to gate 34 which has a source of positive potential 34d connected to the upper end of resistor 34a. In event both rectifiers 34b and34c are cut off, this positive potential will cause current to be applied to wire E and therefore to the input of the magnetic amplifier.35. However, if either one of the rectifiers 3412 or 340 is conducting, the wire E is efiectively grounded. Referring first to rectifier 34b, if the secondary of pulse transformer 33b has an induced potential exactly equal and opposite to that of bias battery 330, the cathode of rectifier 34b is grounded and there is no potential on wire E. Similarly, if there is no potential in the output of delay means 36, the wire H is effectively grounded through primary 3212 as well as resistor 36a, whereby wire E is at zero potential. However, if there is positive potential at the output of delay means 36 concurrently with the absence of output on secondary 33b} the cathodes of'both rectifiers 34b and 340 will be held at a substantial positive potential and hence the potential on wire B will rise to a substantial positive value.

The inverter 33 functions in like manner to the in verter 32. In the absence of potential in the secondary 3311, the bias battery 33c supplies positive potential to the cathode of rectifier 34b. However, when a step input pulse appears on wire B, current flowing through pnimary 33a induces a squarewave pulse into secondary 33b which neutralizes the potential of the battery 33c and effectively grounds the cathode of rectifier 34b.

There has been hereinabove described the function of the parts 30 to 37 inclusive in combination with each other, this description being given with particular reference to Figure 3. There has also been given a description of each individual component part with particular reference to Figure 3B. From these two descriptions, anyone skilled in the ant can fully understand the detailed functioning of the complete circuit diagram of Figure 3B. Figure 4 is a modified form of the invention in which the inverter 32 is replaced by two inverters 42aand 42b.

Otherwise the construction and mode of operation is pre' to have another inversion by inverter 42a at the input of gate 44. l a

The-

Figure is a further modified form of the invention in which the step input 50 feeds gate 51 and inverter 52. The latter feeds another gate 53. So far as the foregoing description of Figure 5 is concerned, it is identical with Figure 3. The only difference between Figure 5 and Figure 3 is that in Figure 5 the delay means 54 appears prior to the amplifier 55 instead of after the same. Otherwise the operation is identical with that of Figure 3.

Figure 6 is a schematic diagram of a modified form of the invention in which sources 60 and 600 of power pulses have outputs as shown in the waveform diagram of Figure 6A. It isnoted in Figure 6A that source 60 and 600 of power pulses are alternating current sources in which the power pulses vary from a positive voltage-of plus V to a negative voltage of minus V. There is, however, a bias battery. 60; in series with power pulse source 66c which causes the power pulses from source 66c to vary about a positive voltage as shown on the lower waveform of Figure 6A. The sources '60 and 69c are synchronized by any suitable means whereby their waveform outputs occur in synchronism and in the relation shown in Figure 6A. The signal input pulses when they appear from source 62 are always timed to occur during a period when the pulses from source 60 are negative, in other words in one or more of the time periods T2, T4, T6, T8 and T10, etc. of Figure 6A.

' Assume that at the start there is no output at the load 60b, in other words, assume that the power pulses from source 60 are encountering high impedance in the coil 60a. In order to accomplish this state, there is a reset current flowing from battery 61 through coil 61a, resistor 61b and battery 6115 during the period between power pulses. Hence, while as shown in Figure 1, the power pulses tend to drive the core from point 14 to point 15, there appears between power pulses a reset current in coil 610: from batteries 61 and 610 which tends to reset the core from point 11 to point 14. Hence, during time period T1, for instance, the core is driven from point 14 to point 15 and returns to zero value of magnetizing force 11 at the conclusion of time period Tl. During time period T2 no current flows from source 60 or 60c due to the rectifiers 60g and 60e, respectively, and

the res e current in coil 61a from batteries 61 and 610 drives the core negatively from point 11 to point 13 on the hysteresis loop of Figure 1. The next power pulse at time T3 drives the core positively from point 14 to point 15, etc. Since under these circumstances the core C is not saturated, there is little output at the load 60b,

or at output 69.

The first pulse from signal source 62 will occur at one of the time periods T2, T4, T6, T8, etc. and will raise the anodes of rectifiers 63d and 61d to a positive value approximately equal to that of battery 61. Hence, no current will now flow in coil 61a. To explain this operation in a little more detail, it is noted that before the arrival of the pulse from source 62, the wire 63m wasat substantially ground potential (even though there is a positive potential on battery 63k) since a current flows from ground through rectifiers 63r and 63d and resistor 62a to negative potential source 62b, whereby the cathode of rectifier63r and hence wire 63m, will be at substantially ground potential. Hence, substantially the entire potential ofhattery 63k appears across the resistor 637'. It follows therefore that a pulse on input 62 will cancel the effect of battery 61 and will prevent the flow of a reset current in coil 61a. During this time interval no current will be flowing through coil 66 and consequently the next power pulse from source 60 (taken with the power pulse from source 600) will saturate the core. This follows from the fact that the core remained at point 11 of the hysteresis loop of Figure 1 during the time period at which the pulse appeared from the signal source 62, and consequently the next power pulse could easily drive the core to saturation from point 11 to point 12.

Since the core is substantially saturated for this particular power pulse, the coils 60a and 60d have low impedance and large currents may flow to the load 60!) and through the rectifier 60c. .A circuit for this current includes battery 65b and resistor 65a. Due to the low winding impedance and the low forward impedance of the diode 60c, a large pulse (negative-going from the +V of source 67a) appears at the connection 69 that is substantially equal to that of the pulse from the source 600. It is noted that during the period when the signal pulse from source 612 raised the potential at the cathode of rectifier 63d to a positive value, the cathode .of rectifier 63c was also being held at a positive value by reason of the bias battery 63a. There was ,no current fl'ow through coil 66, during th'e'time when signal pulses were emitted by source 62, by reason of the fact that the positive pulse from signal source 62 passedthrough rectifier 63e and brought connection 63p to a positive value about equal to that of battery 66b. cumulatively, battery 6311 was passing a current through resistor 63b, rectifier 63f, resistor 63g, and battery 6371, to place point 63p at a positive value approximately equal to that of the battery 66b. Hence, there was no potential across coil 66.

As heretofore stated, one time period folowing the signal pulse from source 62 the coil 69d acquired low impedance and a large negative-going power pulse passed positive potential of battery 63a and consequently the potential of wire 63q was reduced substantially to ground level. Assuming that there was no input pulse from source 62 at this time period, current will then flow from battery 66b, coil 66, rectifier 66a, resistor 63g, and battery 63h. This current, flowing through coil 66, will exactly neutralize the magnetizing force of the reset current then flowing through coil 61a, hence again the core will not be reset during the time period during which signal pulses may appear. As a result, the next power pulse at time period T5 will again flow through coil 60d which then has low impedance to the delay line 64 and will again prevent resetting of the core during time period T6 in like manner to the way the previous power pulse prevented resetting of the core during time period T4. This state of affairs will continue as long as no further pulses appear from the signal source 62 and there will be an uninterrupted train of output pulses at load 60b and also at the negative output 69. The next time a pulse appears from the signal source 62 it will place a positive potential on connection 63p and block flow of current in coil 66 whereby during the time period of this pulse the core will be reset by the current in coil 61a. Such current will flow in coil 61a since point 631 will be substantially at ground potential and will therefore hold wire 63m substantially at ground potential. Consequently, the device will revert to its first stable state in which during the period of the power pulses they will drive the core from point 14 to point 15 and during the interval between power pulses the reset current will drive the core from point 11 to point 13. Hence, there will be no substantial output. During the signal period immediately following the appearance of the second input pulse from source 62, there will be no output at 69, hence battery 63a will be connected to the cathode of rectifier 66a through the resistor 63b and rectifier 63 and will place a positive potential on the cathode of rectifier 66a which is substantially equal to the potential due to battery 66b, wherefore coil 66 is again inoperative. This stable state in which there is no output will continue until another pulse is received on input 62 which will have the same effect as the first-named pulse received there, with like effect. As in the case of Figure 3, there will be a series of output pulses in the load 60b for every two pulses from the signal source 62.

Resistor 65a, battery 65b, rectifier 67 and battery 67a, constitute a sneak suppressor circuit for neutralizing any small pulse current that may tend to flow through coil 60d during a period when that coil has high impedance. Battery 65b has a potential greater than +V but rectifier 67 and battery 67a limit the potential on wire 69 to a maximum potential of +V. The small current flowing due to the difference in potential of batteries 65b and 67a will neutralize any sneak current that will flow through coil 60d while the latter has high impedance.

Resistor 62a and batery 62b maintain a current flow through rectifier 63d along the path 63k-63j-63d 62a-62b. The gate 63c, 63d, therefore does not allow current to flow from battery 63k to coil 61a when input pulses are not being emitted from source 62.

Rectifier 63r prevents the anodes of rectifiers 63c and 63d from going negative.

Figure 6B is a logical (or block) diagram of the apparatus of Figure 6. The several blocks of Figure 6B are marked with the reference numerals of the component parts of Figure 6 composing that block.

In connection with inverter 2 it is noted that this is part of the magnetic amplifier itself, since the battery 60 places a positive bias on source 600, and the latter causes output pulses to go negative from the level of battery 601. This is the equivalent of a magnetic amplifier plus an inverter. Likewise, the part 66 is the equivalent of an inverter at the input of the magnetic amplifier. Otherwise the block diagram of Figure 6B is obvious and needs no further discussion.

Figure 7 is a magnetic counter circuit very similar to that of Figure 6 except for the feedback circuit. At the start of the operation of the apparatus of Figure 7, wire 730 is positive, being so held by batteries 74b and 76. Reverting current passes through the upper half of coil 71 by way of battery 71c, the upper half of coil 71, resistor 71c, and battery 71d. Hence, during the spaces between the application of successive power pulses to winding 72a, the core is reverted so that the next power pulse cannot drive the core to saturation. Therefore power pulses occurring prior to the first step input pulse find winding 72a one of high impedance and hence very little current flows from the source 72b to the output 720. Consequently, there is substantially no charge placed on the feedback condenser 7311 by the power pulse.

If we now assume that the first step input pulse arrives at '70, the upper gate 70a-70c will be open since there is positive potential on both wires 70 and 730. Consequently, current from battery 702 is applied to the anode of rectifier 71a substantially at the potential of the input pulse. There are then substantially equal positive potentials on both ends of the upper half of coil 71 and no current flows through this half of that coil. Accordingly, the core is not reverted during the spaces between power pulses. It follows that the next power pulse from source 72b will find coil 72:: having low impedance, hence the pulse will flow to the output 720 and will also flow through rectifier 73 raising the upper plate of condenser 73a to a positive value. When the power pulse from source 72b ceases, the negative potential of battery 750: will tend to lower the positive potential on the upper plate of condenser 73a drawing the potential of the lower plate of that condenser down also, and thus drawing current from battery 74b through resistor 74a and rectifier 73b to the lower plate of condenser 73a. The flow of current through resistor 74:: will result in a drop in the potential of wire 730. It is noted that rectifier 76a and battery 76 are so connected that they merely act as a limiter to prevent potential from rising above that of the battery 76. Hence, no current flows from battery 76 during the aforesaid operation. The current In this case, rectifier 75c will have a net current in it, and the cathode of said rectifier will be at substantially ground potential.

At the time of this operation it is noted that the potential on both input 70 and wire 73c approached ground potential and therefore the potential at the cathode of rectifier 71b and at the anode of rectifier 71a is substantially ground potential. This follows since the positive potential of battery 70c appears across the resistor 70 and the potential of battery 70g appears across the resistor 7611. In this case, there will be substantially equal and opposite currents flowing through the two halves of coil 71. A current will flow through the upper half of coil 71, as follows: battery 71c, upper half of coil 71, resistor 71c, and battery 71d. This follows since the rectifier 71a is cutoff, its anode being effectively at ground potential. Current also flows from the battery 71c through the lower half of the coil 71, rectifier 71b, resistor 70h, battery 70g, to ground. Consequently, the magnetizing forces of the two halves of coil 71 cancel each other and therefore the power pulses from source 72b flowing through coil 72a will repeatedly saturate the core, giving a continuous series of output pulses at output 72c. This will continue, that is, these output pulses will continue to charge the upper plate of condenser 73a during each pulse. Likewise following each power pulse the upper plate of the condenser will be drawn to substantially ground by battery 75a, thus causing a current to flow through resistor 74a drawing wire 73c substantially to ground potential.

The next or second step input pulse at 70 will raise the potential at the anode of rectifier 7% which will make the cathode of rectifier 71b positive, thus cutting off flow of current through the lower half of the coil 71. Looking at this latter action in another way, it may be noted that the upper end of resistor 7 llh is rendered positive by the input pulses 70, wherefore both ends of the lower half of the coil 71 are at positive potentials so substantially no current flows. Hence, the flow of current through the upper half of coil 71, resulting from batteries 71c and 71a, will reset the core during the periods between power pulses and consequently power pulses from source 72b will encounter high resistance in coil 72a and there will thus be substantially no output at 720. The small current produced in 720! by the power pulse when 72a has high impedance is prevented from appearing in the output 720, as follows.

The current flow from battery 75a through resistor 75b and rectifier 750 will tend to hold the cathode of rectifier 73 at substantially ground potential and therefore any small pulse on output 720 will flow through rectifier 73, resistor 75b and battery 75a to ground, and if the current from 75a exceeds the small current produced by the power pulse, a current will continue to flow in rectifier 75c, maintaining the cathode thereof, and hence the output potential, substantially at ground potential. Since there is no output at 72c the wire 730 will rise to the potential of battery 76. Rectifier 71b will therefore remain cut off and the current flowing in the upper half of coil 71 will reset the core during the spaces between power pulses, inhibiting output at 720.

The aforesaid second step input pulse stopped all output at 72c. Thereafter the apparatus remained in a condition in which there was no output. The third step input pulse at '70 will cause the same chain of events as the first one, and the fourth step input will have the same,

effect as the second one, etc. It, therefore, follows that there will be an uninterrupted train of pulses at output 72c for every other pulse appearing at input 70.

Reference is now made to Figure 8 which has two sources of power pulses, 82b and 82d, which respectively have pulse outputs of the type shown in the upper and lower timing waveform diagrams of Figure 6A. However, in Figure 8, the step input pulses are fed to input 80 at a time period simultaneously with the appearance of power pulses instead of at a time period between power pulses. In other words, the input pulses of Figure 8 would be fed at one or more of the times T1, T3, T5, T7, T9, etc. of Figure 6A.

In Figure 8 the condition of the apparatus immediatey prior to the application of the first step input pulse is as follows: current from battery 82 flows through coil 82g, resistor 85 and battery 85a and resets the core during the spaces between power pulses. Hence, when the power pulses arrive they find that coils 82a and 82a have high impedance and hence there is very little current flow through these coils. Moreover, at the time of the first input pulse at input 80, the battery 810, operating through resistor 81, holds the anode of rectifier 86d and the cathode of rectifier 8% at a high positive potential determined by battery 8%. This conditions the upper gate 80a-80b so that when a step input pulse appears at input 80 and raises the potential of the cathode of rectifier 80a, current can now flow from battery 80; through resistor 80: and will be impressed upon rectifier 83a, delay line 83 and rectifier 83b at the input pulse potential, this will cut off further flow of the reset current which is otherwise passing through coil 82g.

It is noted that the delay line 83 delayed the pulse by onetime period. In other words, if the step input pulse appeared at time period T1 of Figure 6A, the delay line 83 delayed the efiect of it until time period T2 and prevented the coil 82g from resetting the core during the time period T2. The next negative going power pulse from source 82d then passes through coil 82e which has low impedance (since the core was not reset during the immediately preceding time period), and thence through rectifier 87 and cancels the positive bias set up at wire 89 by battery 89b. Normally the positive bias of battery 8% is applied to the cathode of rectifier 80b as aforesaid, but since the pulses from source 82d are negative going, as shown in Figure 6A, they effectively cancel the aforesaid bias of battery 8%. Hence, the upper gate is effectively cut off since current may readily flow through rectifier 80b to Wire 89 which is now substantially at ground potential. During this latter event, the potential of battery 80f appeared across resistor 80a. The potential at the anode of rectifier 80d was lowered to substantially ground potential and therefore this rectifier did not prevent current from flowing from battery 80h, to resistor 80g, to rectifier 84a, delay line 84', rectifier 84b, winding 821', and battery 82h. The delay line 84 delayed this pulse by one time period and therefore it arrived at the winding 82 during a space between power pulses, in other words, at one of the times such as T2, T4, T6, T8, etc. of Figure 6A, and the delayed pulse cancelled the magnetizing force of coil 82g during one of the said periods. Hence, the power pulses which are emitted by sources 82b and 82d during the next time period will pass through coils 82a and 82e which then have low impedance. Consequently, there will be an uninterrupted train of power pulses at the output 88 until, as described below, another pulse appears at the input 80.

The next step input pulse at input 88 raises the potential at the anode of rectifier 800 to a positive value and allows current to flow from the input 80 through resistor 86g and battery 80h. The potential of the input pulse appears as a drop across resistor 80g and consequently the upper end of resistor 80g is no longer at ground potential and consequently current ceases to fiow through coil 82j. Therefore the reset current which flows through coil 82g from battery 827 will reset the core during the period between power pulses and consequently the next power pulse will not produce a substantial output. The step input pulse. ceases. before the next power pulse. The

12 next negative going power pulse from source 82d will find winding 82e with high impedance and consequently. the point '89 will no longer be driven to a negative value and will again assume a positive value by reason of batteries 81a and 8%. Consequently no further current will flow from either the upper gate 8tla80b or the lower gate 8tlc8fid to either of the windings 82g or 821'. The upper gate will remain out off since current will flow from battery f, resistor 780e, rectifier 80a, resistor 80 and battery 88k. Hence, the potential of battery 80 will appear across resistor 88c and there will be no positive potential at the anode of rectifier 80a which will be at substantially ground potential. Likewise, the anode of rectifier 880 will be at ground potential (since the step input pulse will have ceased by this time) and therefore no current will ilow from the cathode of that rectifier through rectifier 84a to coil 82 Hence, the apparatus will continue to operate in the condition whereby the current from batteries 82 and 85a resets the core through coil 82g during the spaces between power pulses, thus rendering the coils 82a and 82e high impedance during subsequent power pulses. This condition will continue until the next step input pulse arrives at input 80 which will have the same effect as the first step input pulse which arrived at input 89. Consequently, there will be a single uninterrupted train of output pulses for every two step input pulses that appear at the input 88. The rectifier 86 prevents the anode of rectifiers 80a and 80b from going negative. Battery 82h has a small positive potential but this battery is not absolutely necessary and may be omitted. Rectifier 89a and battery 8% constitute a sneak suppressor which neutralizes any sneak currents tending to flow toward point 89 from source 82d during periods when coil 82a has high impedance. The potential of battery 840 is about equal to that of battery 89b and serves simply as the equivalent of a ground return for the terminating resistor 84d of delay line 84. From another point of view, since the outputs from 82e are negative going from a positive level, it is necessary to refer the delay line to approximately the same positive level.

Figure 9 is a schematic diagram of a modified form of the invention in which there is a feedback connection that includes a second magnetic amplifier. Figure 9A is a timing wave-form diagram of the several power and blocking pulse generators 90a to 90c inclusive of Figure 9. Prior to the first pulse, we will assume the following state of the several component parts of the apparatus: Pulses will flow from pulse generator 90a through coil 92a without substantial impedance, since neither of coils 92b nor 920 have reverting currents flowing therein. The heavy current flow through coil 9.2a will pass through rectifier 940 to coil 94d and will repeatedly reset core 94 during the spaces between the power pulses of generator 98d, whereby there will be very little output current from pulse generator 90d flowing through coil 94a. Consequently, since there is little output from pulse generator 94a, the battery 95'will raise the potential on wire 97 to a positive value determined by battery 96. This will place a positive potential 011 the cathode of rectifier 911; thus enabling the upper gate to have an output whenever a step input pulse appears at input 91. The positive potential on the anode of rectifier 910? will cause current to flow therethrough, thereby raising the potential of the anode of rectifier We and will prevent substantial current flow through the coil 920 during the spaces between the power pulses of source 90a. The latter result follows from the fact that the two ends of winding 920 each have applied thereto substantially equal positive potentials, during the spaces between positive power pulses from 90a, the left end deriving its potential as hereinabove described, and the right end deriving its potential from the pulse source 900, hence no current can flow from the positive pole of source 90c through rectifier 92a because the latter rectifier is substantially biased oil as hereinabove described.

blocking pulse during the periods between the positive pulses of source 9011. The purpose of the positive pulses of source 90a is to prevent any flow of current through coil 94d due to the voltage induced therein by the current flowing in winding 94aduring the time that voltage from the source 90d is at ground level as shown in Figure 9A. It will be observed that source 90d may be any suitable source capable of an output having the waveform shown at the bottom of Figure 9A. The source 90d is connected with its positive pole in contact with the positive pole of the battery 94]. Moreover, the source 90d has a maximum potential approximately equal to that of battery 94f. Hence, whenever a pulse appears from source 900? it neutralizes the potential of the battery 94;) and the combined potential of battery 94 and source 90d is zero. However, the change in current in coil 94a which results from the pulsing of source 90d tends to induce a voltage in coil 944 in such a direction as to cause current to fiow therein. Also there may possibly be leakage currents flowing through rectifier 940 into coil 94d. The purpose of pulse generator 902 is to provide a large positive pulse during the period of the pulses of source 90d which will bias rectifier 940 so as to prevent current flow therethrough.

With the foregoing background, assume that the first step input pulse arrives at wire 91 at a time between two positive power pulses of source 90a. The potential at the cathode of rectifier 91a will now rise and a reset current will fiow from battery 912 through coil 92b during the space between two of the positive power pulses emitted by source 90a. The'sole purpose of the pulse generator 90b is to produce blocking pulses in the same way and with like effect to the blocking pulses produced by source 902. Since the signal pulses always occur during the spaces between positive power pulses of source 90a, the blocking pulse generator 90b will be inoperative during this period and will therefore not prevent the output at the upper gate from resetting the core through coil 92b. Since the core is reset during the space between two of the power pulses from source 90a, the second of these power pulses will meet high impedance in coil 92a and will not cause a current to flow through the rectifier 94c and consequently the core 94 will not be reset during the space between the pulses of source 9001. The next power pulse from source 90d will neutralize the eifect of battery 94] and consequently there will in effect he a connection of substantially zero resistance between the upper end of coil 94a and ground. Consequently, current from the battery 95 will tend to flow through resistor 95a, rectifier 94b, coil 94a, to ground. Most of the drop will occur across resistor 95a and this will reduce the potential on wire 97 to substantially ground potential. Consequently, current may now flow from pulse generator 900 through coil 92c, rectifier 92e, resistor 91g, and battery 91h to ground, whereby there is a reverting current in coil 92c. There is no reverting current in coil 92b during this period since the upper gate is cut off due to the fall in potential on wire 97. The reverting current in coil 920 causes the next power pulse from source 9011 to meet high impedance in coil 92a so it will not pass current to the coil 94d. Hence, the core 94 is not reverted and current may therefore flow from battery 95 through the coil 94a to ground whenever there is a negative pulse from source 90d counteracting the potential of battery 941. Consequently, during the periods'when signal pulses may be expected, the potential on wire 97 repeatedly drops to ground potential and therefore there are no reverting currents in coil 92b, but there are reverting currents in coil 92c, hence no outputs from coil 92a. This condition continues until the second step input pulse is received at 91 which has the effect of placing a large positive potential at the anode of rectifier 91c thus raising the cathode of that rectifier to a positive value and preventing flow of current from the source 90c through coil 92c. Hence, the core 92 is not reverted during the spaces between power pulses from source a and the next power pulse from source 90a will fiow through coil 94d and revert the core 94 so that it will present high impedance to the next pulse that tends to flow through coil 94a. Hence, when in fact the next power pulse from source 900! arrives, it will, as previously, cancel the elfect of battery 94], but when the current begins to flow from battery through coil 94a it will meet high impedance in the coil 94a and consequently the potential on wire 97 will remain at the potential of the battery 96 instead of drop-ping to substantially ground potential as previously. This positive potential on wire 97 will prevent coil 92c from reverting the core in the way heretofore mentioned and since there is no step input pulse at input 91, the coil 9212 will not revert the core 92 and consequently power pulses from source 90a will continue to cause current to flow through coil 94d. Likewise, coil 940: will continue to present high impedance to the current from the battery 95 and consequently the wire 97 will remain at the potential of the battery 96.

The third step input pulse at 91 will start the same chain of events as the first one and will therefore pass reverting current through coil 92b and stop the flow of power pulses from source 90a to coil 94d wherefore the coil 940 will present low impedance to pulses from the battery 95 and the potential on wire 97 will drop to substantially ground potential.

The fourth step input pulse on input 91 will have the same effect as the second step input pulse and will revert the apparatus to the second of its two stable states. It is noted that in one stable state the pulses from source 90a supply current to the load 93 through rectifier 93a. Hence, there is an uninterrupted train of pulses starting with the power pulse next following the second step input pulse and continuing until the third step input pulse. Between the second and third step input pulses there will be outputs at the load 93. Between the third and fourth step input pulses there will be no pulses arriving at the load 93.

During the intervals when there is high impedance in the coil 92a a small current might tend to flow from the pulse generator 90 to the winding 94d and to the load 93. In order to prevent such current flow, a battery 93c is provided along with resistor 93d and. rectifier 9311. These components tend to pass a current through the load 93 in exactly the opposite direction to the small snea current which tends to flow through coil 92a dur ing the high impedance periods thereof. However, the rectifier 93b is provided and so connected as to conduct the current flowing from battery 930 through resistor 93d to ground. The said small current in winding 92a has the elfect of reducing the current in rectifier 93b; and the current supplied by battery 93c may in fact be so chosen by selection of resistor 93a that the said small sneak current is the lesser of the two, wherefore the cathode of rectifier 93b will remain substantially at ground potential in the presence of the said small sneak current, without however substantially impeding the fiow of output current through winding 92a to the load 93 when winding 92:: is of low impedance. Hence, these so-called sneak currents are compensated for by the battery 930, et al.

Figure 10 is a schematic diagram of a modified form of the invention using two magnetic cores 100 and 101. The timing waveform diagram of Figure 10A illustrates the waveforms of the various sources of power pulses of Figure 10. The magnetic amplifiers or transformers 100 and 101 operate in a somewhat diiferent fashion from those of the other figures, and consequently a detailed description will be given.

Referring first to core 100, it is noted that it has coil 100a connected to source of power pulses 100d through rectifier 100e. There is a resetting winding 100i) and a secondary output winding 100a. Assuming that prior to any given power pulse the core is operating at point 11 on the hysteresis loop of Figure 1, the next power pulse from source 100d will drive the core to point 12 and there will be very little flux change in core 100* and consequently very little potential induced in coil 100a. The next power pulse will have the same effect. As long therefore as the core continues to operate on the saturated portion thereof, the induced potential in the secondary coil 100a will be very small.

On the other hand, if during the period between two power pulses from source 100d, current flows through reset coil 100b, the core will be driven from point 11 to point 13 on the hysteresis loop of Figure 1. The next pulse from source 100d will then drive the core primarily along an unsaturated portion thereof from point 14 to point 15 on the hysteresis loop of Figure 1, producing a large flux change in the core 100, and therefore a large potential will be induced in secondary coil 100a. In other words, if there are a series of resetting pulses in coil 10017 occurring during the spaces between power pulses from 100d, there will be a series of large output pulses from secondary 100a. On the other hand, if there are no resetting pulses in coil 100]), the pulses from source 100d will drive the core to saturation during each pulse and there will be very little output in the secondary 100a. Source 100g produces blocking pulses and normally does not enter into the operation of the device except merely to prevent current flow in reset coil 100!) during time intervals when such current is not desired. For example, pulses to reset coil 1005 are supplied by the secondary 101a of core 101. The pulses from coil 101a normally occur during the spaces between pulses from source 1001?. (since they are due to pulses from source 101d) as shown in Figure A. In order to prevent the voltage induced in reset coil 100i: due to the power pulses 100d from producing current in coil 10011, the blocking pulse generator 100g emits positive pulses which tend to cause current to flow through reset coil 10% but such current may not so flow due to rectifier 107 which is connected in the opposite direction to permit pulses from source 100g to flow. Therefore source 100g merely opposes or neutralizes any voltage that will tend to be induced in coil 10% due to current in coil 100C.

The magnetic transformer 101 operates in a manner quite similar to that of transformer 100. It has a secondary coil 101a, a reset coil 103% and a primary winding 101C. The primary winding is fed by a source of power pulses 101d through rectifier 101a. The relation of the power pulses of source 101d and those of source 100d is shown in Figure 10A. In order to prevent flow of current in the reset coil 101b, due to induction from coil 101e, the blocking pulse generator 101g may be employed. Its polarity is such that current therefrom may not flow due to the rectifiers 105 and 106, which prevent such flow. Hence, if during any given power pulse from source 101d a voltage is induced in coil 101b, the blocking pulse generator 101g will oppose or neutralize any such voltage and prevent current from flowing in the input circuits of the apparatus.

The function of the lower gate (104 to 10%) will now be explained. In the absence of a step input pulse at 102, current will flow from battery 104 through resistor 104a, resistor 104d and rectifier 1040 to battery 104s. The voltage of batteries 104 and 104:: and the values of resistors 104a and 104d are so chosen that in this case a current will also how from ground through rectifiers 104k and 104s and resistor 104d to battery 104a. Hence, the anode of rectifier 106 and wire 104m connected thereto will be at substantially ground potential. if there is no input pulse through the primary winding 104g of pulse transformer 10 4-1, the battery 104 will place a positive potential on the cathode of rectifier 10%. If then a pulse is received at step input 102 without a pulse being simultaneously received in primary 104g, the upper end of resistor 104d will be raised to a high positive value,

16 rectifier 1040 willbe cut off and a current from battery 104 will be placed on output lead 104m substantially at the potential of the input pulse at 102. Therefore an output pulse will appear in wire 104m which will 'flow through rectifier 106 and reset coil 10117 to ground.

On the other hand, if a pulse on the step input 102 is received concurrently with a pulse in the primary 104g of pulse transformer 104f, there will be no output at wire 104m for the reason that the potential induced in secondary winding 104/1 will be substantially equal and opposite to that of battery 104i, thus grounding the cathode of rectifier 10412. If rectifier 104b is effectively at ground potential, it will hold wire 104m at ground potential and there will be no output pulse.

The two pulse transformers 1037 and 104] are of the well known type which has a substantially square wave output across the secondary when a square wave is ap' plied to the primary.

The operation of the upper gate (103 to 103k inclusive) is substantially identical to that of the lower gate (104 to 104k inclusive). In the absence of input pulses on wires 102 and 109, the potential at output wire 103mof the upper gate will be zero. This follows from the fact that batteries 103 and 103 have potentials so related to the resistances of resistors 103a and 103d that current will flow from ground through rectifiers 103k and 10312 and resistor 103d to battery 103i, leaving the cathode of rectifier 105 and wire 103m at substantially ground potential. The cathode of rectifier 1030 will be held at a substantially positive potential due to the battery 103k, in the event there is noinput in the primary winding 103a of the pulse transformer. Hence, in the absence of energization of the primary of the pulse transformer, rectifier 1030 will be cut off. If then a positive pulse appears on wire 109, the cathode of rectifier 103b will rise to a positive value and current from battery 103 will be impressed on wire 103m substantially at the potential of wire 109 and current may then flow through rectifier 105 to reset coil 101b.

If, however, a pulse appears on wire 109 simultaneously with the step input pulse on wire 102', there will be no output at wire 103m because the step input pulse will induce a potential in the secondary 103g which is equal and opposite to the potential of battery 103k, thus effectively grounding the cathode of rectifier 103e, thereby effectively grounding the wire 103m- Hence, the operation of the upper gate may be summarized by stating that there will be an output pulse on wire 103m wherever there is a pulse on wire 109 except during those intervals when there is a pulse in the primary 103e simultaneous with a pulse on wire 109.

With the foregoing background, it is now possible to explain the normal idle condition of the apparatus which prevails at the time that the first step input pulse is received. Prior to the first step input pulse there is no potential on either of wires 103m or 104m and consequently no current flow in reset coil 101b. Hence, the pulses of source 101d repeatedly saturate the core 101 and there is no output in secondary 101a. It follows that there'is no input to the reset coil 10% of core and that consequently the pulses from source 100d repeatedly saturate the .core and there is accordingly no potential induced in the secondary 100a. Consequently there is no current in either of outputs 108 or 109. It follows therefore that there is no current flowing in primerry-104g and that the cathode of rectifier 104b is biased to a positive value by battery 104i and therefore is cut off. It then we assume that the first step input pulse is received on wire 102, it will raise the potential of the cathode of rectifier 1040 to a positive value, thus allowing battery 104 to place a positive potential on wire 104mwhich will cause current flow through rectifier 106 and reset coil 1011; to ground. The core 101 will therefore be reset during the interval between power pulses of source 17 101d and the next power pulse will induce a current in secondary winding 10111 which will produce a current flow in reset coil 1001: during spaces between power pulses of source 100d. The next power pulse from source 100d will induce current in secondary winding 100a which will produce output pulses in wire 169 and in primary winding 104g. If during the time of a pulse in primary 104g another step input pulse is received at 102, it will have no effect on the output 104m whichwill remain at zero. If there is no step input pulse at 102 at the time of the pulses on wire 1119 due to the current induced in secondary 100a, the upper gate will be biased to allow current from battery 103 to flow to wire 103m and thus again feed reset coil 1011b. Consequently if we assume that no further step input pulses are received following the first one, there will be a recycling of the apparatus since the output of secondary 100a will feed pulses through wire 109 to the cathode of rectifier 103b thus cutting off this rectifier and allowing pulses to flow from battery 103 through wire 103m and reset coil 101b. This will continue to reset core 101 and allow power pulses from source 101d to induce current in coil 101a which will pass current in reset coil 1110b and thus reset core 100 whereby the power pulses from source 100d will continue to induce current in secondary 100a which will continue to feed current to wire 109 which will continue to open the upper gate to the flow of further current from battery 103 to wire 103m, etc. This recycling will continue until the next input pulse is received at 102 and during this recycling output pulses will appear on wires 1118 and 109 but in different phases.

If it now be assumed that at some later time the second step input pulse is received at wire 1112, it will cut off the upper gate and since the lower gate is already cut off there will be no potential on either of wires 103m or 104m. The upper gate will be cut off by reason of the fact that the step input pulse will induce potential in the secondary 103g which is substantially the equal of, and is opposite to, the potential of battery 103k whereby the cathode of rectifier 1030 is effectively grounded, hence wire 103m is elfectively grounded. There will be no potential in wire 104m at this time because simultaneously with the step input pulse there will have been a pulse on wire 109 which will have induced a potential in secondary substantially the equal of, and opposite to, the potential of battery 104 thus effectively grounding wire 104m through rectifier 1114b. Consequently there will be no current flow through reset coil 101b and the core 1131 will be saturated by the next power pulse from source 101d. Therefore there will be no output from secondary 101a and no reset current in coil 1011b. Consequently the next power pulse from source 109d will saturate the core 100 and there will be no output from secondary 100a and therefore the pulses on both outputs 108 and 109 will stop.

Assuming that this second power pulse is not followed by any subsequent power pulses for a considerable period of time, then both the upper and lower gates will remain inoperative. The lower gate will remain inoperative since the cathode of rectifier 1040 is at substantially ground potential in the absence of input pulses, hence wire 104m is at substantially ground potential. :Likewise, the upper gate will hold wire 103m at substantially ground potential since the potential drop across resistor 103a is equal to the potential of battery 103 and the potential drop across resistor 103d is equal to the potential of battery 103 In other words, both the upper and lower gates will be cut 011 for the same reason that they were cut off before the first step input pulse was received. This condition will continue until the third step input pulse is received which will have the same efiect as the first step input pulse. Likewise the fourth step input pulse will have the same effect as the second one. It follows therefore that after the first step input pulse there will be an uninterrupted train of power pulses on wires 1118 and 109 continuing until the second step input pulse. Following the second step input pulse, there will be no pulses on wires 108 and 109 until the third step input pulse is received, at which time there will again be an uninterrupted train of output pulses on wires 108 and 1119 until the fourth step input pulse is received, etc. Consequently, there will be a single uninterrupted train of output pulses on wires 108 and 109 for every two step input pulses on wire 102.

Figure 11 is a block diagram of a modified form of the invention which differs from the others .in function, in that there must be a predetermined time spacing between two step input pulses in order for the second one of the two to be effective. The apparatus uses gates, inverters, and non-complementing amplifiers of the type already described.

When the apparatus is in the normal position awaiting the first pulse, there is no input to the inverter 112 and consequently it is enabling gate 111 so that the latter will pass any step input pulses on wire 110. Upon arrival of the first input pulse, gate 111 is open, allowing the pulse to pass to the non-complementing amplifier 113. Hence, the next power pulse fed to this amplifier passes therethrough to the output 119 and also to the delay line 114. This delay line delays the pulse by one-half period, which means that the delayed pulse will pass through the gate 115 and arrive at the input of non-complementing amplifier 113 during the signal pulse time period thereof and will therefore so trigger the non-complementing amplifier that the next power pulse will travel therethrough to the delay line 114 and gate 115 in time to constitute another signal input pulse that will again trigger the non-complementing amplifier so that the next following power pulse will pass to the delay line 114, etc.; and consequently the apparatus will continue in this stable state, giving an uninterrupted train of output pulses at 119. The output of the delay line 114 is fed to the long delay line 116 which triggers gate 117. Gate 117 is open only when it is simultaneously energized by both the output of the long delay line and by a step input pulse from 111). When signalsfrom both of these sources occur simultaneously, gate 117 allows current to flow to inverter 118 which, due to its inversion properties, inhibits the gate 115 and therefore stops current flow therethrough.

The second input pulse at will tend to stop the cycling operation heretofore described, but only if it occurs after a given period of time from the first input pulse. Until the first input pulse has triggered noncomplementing amplifier 113 and outputs therefrom have passed through delay line 114 and delay line 116 to inverter 112 and gate 117, the gate 117 remains closed and will therefore not function in response to a second step input pulse. However, if the second step input pulse arrives at a sufficient time period after the first one, the first pulse will have triggered the non-complementing amplifier, outputs therefrom will have passed through delay line 114 and long delay line 116, and will have opened gate 117 so that the second pulse will pass through the gate 117 and inverter 11%, thus stopping the triggering of gate and stopping the flow of the recycling current through gate 115 and hence stopping the recycling operation. Hence, there will be no output pulses at 119. Preferably the long delay line should delay the signals fed therethrough by an integral multiple of the period of the power pulses.

The third step input pulse must likewise follow the second one by said predetermined time period, otherwise it will not be operative to restart the recycling operation. For a'predetermined time after the cessation of the recycling current resulting from the opening of gate 115, there will continue to be pulses at the output of the long delay line 116 which will be inverted at the inverter 112 and consequently there will be no triggering input pulses to gate 111 and consequently this gate will not be recep- 

